Circuitry for detecting the difference in phase and frequency between two digital input signals has general utility in signal analysis and is of particular importance in digital communications and frequency synthesis. In a digital phase locked loop, for example, an input signal is applied to a phase detector for comparison with a reference signal. An error signal, which is a function of the instantaneous phase/frequency difference between the input signals, is filtered and applied to control a voltage controlled oscillator (VCO). The output of the VCO, which constitutes the output of the phase locked loop, is applied as the reference signal to the phase detector to cause the phase/frequency of the VCO to "lock" to the phase/frequency of the input signal. In some applications, phase locked loops are used for signal demodulation as discussed in Gardner, Floyd M., Phase Lock Techniques, Second Edition, 1979, John Wiley & Sons, Chapter 9. In other applications, phase lock loops are used for signal modulation (Gardner, Chapter 9, supra) or in frequency synthesis as described in Erps et al U.S. Pat. No. 4,360,788, assigned to the assignee of this invention.
In any case, a conventional digital phase/frequency detector comprises a pair of flip flops or other bistable devices connected together and with a logic gate in a feedback circuit. The logical states of the two flip flops are determined both by the two digital input signals whose frequency/phase difference is to be detected and by the logic gate. With the flip flops initially reset, the data terminals of both are connected to a logic "1" and the clock terminals are connected respectively to the two input digital signals. The output of each flip flop is set to a logic "1" upon detection of a positive transition of its input signal. Thus, if the input signal applied to the first flip flop has the first positive transition the first flip flop is set to a logic "1" and thereafter, the second flip flop, upon a positive transition, by its input signal, becomes set to a logic "1". Immediately after the second flip flop becomes set, however, both of the flip flops are reset by the logic gate which responds to the outputs of the two flip flops, and both remain reset until one flip flop or the other detects a positive signal transition of its input.
The outputs of the two flip flops thus are square waves having duty ratios that correspond to the phase/frequency difference between the two input signals. If the first signal leads the second signal, only the first flip flop develops a square wave, with the duty ratio corresponding to the amount of phase/frequency lead between the two input signals. If the second input signal leads, only the second flip flop develops a square wave with a duty ratio that corresponds to the amount of phase/frequency lead of the second input signal relative to the first. The two square waves are combined in a difference circuit and the resultant is integrated to obtain a sawtooth centered about zero, that is, the sawtooth has one polarity when the first input signal leads and the opposite polarity when the second input signal leads. The sawtooth has an amplitude that corresponds to the phase/frequency difference between the two digital input signals and has a fixed period of 360.degree.. As the phase/frequency difference between the two input signals increases monotonically, the output of the detector is a sawtooth train having a number of sawtooth cycles that corresponds to the number of full cycles of phase/frequency difference between the two digital input signals.